Tools info

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Commonly encountered LVS and ERC warning in Calibre (Mentor Graphics)

Document mailed to Vishal from Coreel Technologies (Mentor Graphics) helping in resolving some commonly found errors in Calibre (Mentor Graphics)
Ambiguity_in_LVS, Corner_case_extraction_using_user_defined_corner, ERC_Path_Check, ERC_Path_to_power_and_ground, Smashed_Devices_warning_in_LVS

Opening Cadence remotely on Hollerith from a local machine


  • Some fonts (75 dpi fonts ?) that Cadence wants seem to be missing in Ubuntu 12.04 and 14.04. Install them manually with this command.

sudo apt-get install gsfonts-x11 texlive-fonts-extra xfonts-100dpi xfonts-75dpi xfonts-100dpi-transcoded xfonts-75dpi-transcoded

Then restart your local machine, log into Hollerith and try launching Cadence. Also, in Ubuntu 12.04, ssh login to hollerith was taking longer than 10 seconds. This issue was fixed by changing the line "hosts: files mdns4_minimal [NOTFOUND=return] dns mdns 4 mdns" to "hosts: files dns" in /etc/nsswitch.conf

  • Launching IC514 can cause the gnome-panel to crash in 14.04.
    Starting it manually also fails
    This seems to be a known bug related to gnome-panel
    Just use an alternative such as unity or xfce.

CentOS 6.2

Here also install X11 75dpi fonts

Xilinx on Ubuntu

Xilinx ISE should install and work fine in Ubuntu. The issue lies in the driver for the Platform USB Cable. A third-party driver solves the problem.

Install these dependencies(with apt-get or yum): libusb-dev fxload

Download the driver source and do as the README says. [1]

This gives an init script that loads the driver at boot. [2]


A data visualization tool for streaming data.


RTL to GDS - Digital tool flow

A template for the RTL2GDS flow. Write verilog code, call the script and you'll get the GDS without having to interact with any of the tools !

RTL2GDS Digital Flow Script

Tutorial on Mixed mode simulation and simulation of spice netlists in Cadence

This tutorial will show you how to simulate a mixed-mode circuit, a circuit partly described by verilog and partly by circuit elements such as resistors, capacitors, transistors etc. in Cadence IC5141. It will also show you how to directly simulate a SPICE netlist without having to create schematic and symbol views in Cadence. The demonstration is made by building a window comparator using two discrete op-amps described by a manufacturer provided SPICE macro-model) and an AND gate(described by verilog).

Link to full tutorial with screenshots

Monte Carlo with UMC13mmrf

Use this model library for LL transistors when performing Monte Carlo analysis.


Specify the section "mc" when performing process and mismatch analysis. Also, specify design variable 'sigma' and set it to 3. Specify section such as "tt" or "ss" or "ff" or "snfp" or "fnsp" for mismatch only simulation (you are fixing the process corner here).