IC615 tutorial

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Beginner's Guide to IC615

For Digital VLSI course projects

Copy the work_cad directory from username "smart" to your /home/ directory via:

cd
cp -r ~smart/work_cad .




Setup environment via:

cd work_cad
csh
source cadence.cshrc

Start cadence schematic editor

ic


Refer to the instructions below to create and simulate your first schematic.
Some deviations for the instructions below:

  • The model libraries do not need changing (for now at least)
  • Transient simulation instructions are not yet updated!

Documentation path: /opt/umc65nmll/G-9FD-LOGIC_MIXED_MODE65N-LL_LOW_K_UMK65FDKLLC00000OA-FDK-Ver.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/doc/



Machine allotment

  • 30: Manjunath
  • 31: Rajib
  • 32: Rohit
  • 33: Saugata
  • 34: Kuruva


  • 35: Pranshu
  • 36: Prateek
  • 37: Opilli
  • 38: -- cadence not working
  • 40: Tara


General instructions

1) Create a folder called cadence6
2) Copy the cadence.cshrc file into your cadence6 directory from /srv/holl/karthikj/cadence6/cadence.cshrc
3) You next need a cds.lib file. All the libraries that you wish to work with, while working on the Cadence Virtuoso will need to be specified in the cds.lib file. As you create new libraries through the GUI interface, the cds.lib automatically gets updated. Here you start with a basic cds.lib which you can copy from

. Place this in your cadence6 folder
4) Invoke c shell by typing 'csh'
5) Source the cadence.cshrc from your cadence6 folder by typing 'source cadence.cshrc'
6) Now you are all set to invoke Virtuoso by typing 'virtuoso'
7) The tool comes up and you will see a windows which looks like this

Image1 Click on Tools --> Library Manager , to bring up the Library manager window.
The Library manager window, you can view a list of libraries on the left.
Click on any of them to view the list of cells that particular library contains.
This list shows up in the 'Cell' pane.
Each of thee cells may also have multiple views such as 'schematic', 'symbol etc
An image of the 'Library Manager' window is shown below

Image2
8) We will now create a new library, which will contain the cells we design.
9) Click on File --> New Library..
Type in the name of the the library. You will then get a window "Technology File for new library".
Choose "Attach to an existing technology library" as shown below.

Image3
Choose "umc65ll" as the technology library in the next window ("Attach library to technology library") that shows up
10) Now we can create new cells in this library we have just created. We will first make an inverter as our first cell.
Go to the Library Manager window.
Ensure that the library you have created is highlighted in the "Library" pane on the left.
Click on File--> New --> "Cell View" .You will get a window as shown below.

image4


Ensure that the libray name is correct, and the view is "Schematic" .
Enter a cell name of your choice . Here we have called it "inv_65".
This will bring up the schematic editor window.
11) Press 'i' on the keyboard to instantiate a cell. Here we will first need to instantiate the NMOS , and PMOS transistors.
"Add Instance" window pops up. Browse to select the library as "umc65ll".
Choose the NMOS transistor to be "N_12_LLHVT". Ensure that the View is set to "symbol".
Place the transistor on the schematic editor window.
Press 'i' again to instantiate the PMOS transistor "P_12_LLHVT".
A snapshot of this instantiation window is shown below

image5
The library name, and cell names for few commonly used cells are listed below, in the format (Lib name, cell name) -
Vdd - (analogLib, vdd)
Ground - (analogLib, gnd)
pulse source - (analogLib, vpulse)
dc source - (analogLib, vdc)
Instantiate the PMOS, NMOS, and the Vdd, and Gnd symbols.
12)We finally instantiate the dc source, "vdc" from the analogLib library.
We will be sweeping this source to find this inverter Voltage Transistor Characteristics.
Set the "DC Voltage " to "vsup" while instantiating this source. We will be sweeping the "vsup" variable to generate the VTC.
A snapshot of this instantiation is shown below
image 6

While the input to the inverter is being swept to generate the VTC, we will need another DC source to hold a constant supply voltage.
Set the "Dc voltage" of this source to 1.2V.
13) Click 'w' to create wire connections between the instances.
Also name the nets at the input and output of the inverter by using'l'. 14) Click on "Check and Save", and ensure that there are no warnings or errors in the schematic. An image iof the completed schematic is shown below -
image7

15) We are now ready to simulate it! From the schematic editor, go to Launch -->ADE L. The "Virtuoso Analog Design Environment" window comes up. We first need to set the Model library. Click on Setup --> Model Libraries. Select all the existing libraries that appear on the list and delete them.
Add "/srv/foundry/UMC/65nm/65nm_ll/Designkits/Cadence_6.1/Models/Spectre/l65ll_v151.lib.scs", and set the section to "tt_ll_hvt12".
Ensure that the section corresponds to the transistors used.
A snapshot of this is shown below -
image 8

16) Go to "Analog design environment ".
Click on "Variables "--> Cope from Cell view . When we do this, "vsup" shows up in the pane on the left . Set its value to 1.2
17) To set to the VTC simulation, click on Analysis --> Choose -->
Select Analysis to be "dc". Select "Sweep variable" to be "Design Variable" , and select the design variable to be sweep . Set the Sweep Range "Start-Stop" to be 0 and 1.2 respectively.
An image of this is shown below.
image 9

18) One last step before simulation is to specify which nets we wish to plot at the end of simulation. For this, go to Analog design Environment window, and click on Outputs -->To be plotted --> Select on Schematic.. Click on the input, and the output nets of the inverter, and they get added to the list of simulation outputs that will be plotted. 19) The final step ! Click on "Netlist and Run" ! The inverter VTC shows up at the end of simulation. A snapshot of the simulation output is shown below

image10

20) We can set the input to the inverter to be a pulse source, and do a transient simulation..

65nm specific info

  • cds.lib entry for IC615:
    DEFINE umc65ll /srv/foundry/UMC/65nm/65nm_ll/Designkits/Cadence_6.1/umc65ll (for LL process)
  • Spectre Model file:
    /srv/foundry/UMC/65nm/65nm_ll/Designkits/Cadence_6.1/Models/Spectre/l65ll_v151.lib.scs section "tt_ll_lvt12" <-- for now at least -- choose based on tx used!



  • cds.lib entry for IC514:
    DEFINE umc65ll /srv/foundry/UMC/65nm/65nm_ll/Designkits/Cadence/umc65ll (for LL process)
    DEFINE umc65sp /srv/foundry/UMC/65nm/65nm_sp/Designkits/Cadence/umc65sp (for SP process)
  • Spectre Model file:
    /srv/foundry/UMC/65nm/65nm_ll/Designkits/Cadence/Models/Spectre/l65ll_v141.lib.scs section "tt_ll_lvt12" <-- for now at least -- choose based on tx used!



130nm specific info

  • cds.lib entry for IC514:
    DEFINE umc13mmrf /srv/foundry/UMC/UMC_L130E_MIXEDMODE_RF_16Jan2011/umc130nm/rf/Designkits/Cadence/umc13mmrf
  • Spectre Model file:
    /srv/foundry/UMC/UMC_L130E_MIXEDMODE_RF_16Jan2011/umc130nm/rf/Designkits/Cadence/Models/Spectre/L130E_HS12_V241.lib.scs section "tt" -- choose based on tx used!

/srv/holl/foundry/130nm/rf_umc_27Oct2012/Designkits/Cadence/Models/Spectre/L130E_HS12_V241.lib.scs section "tt"-- choose based on tx used!

  • Monte carlo model file:
    /srv/foundry/UMC/UMC_L130E_MIXEDMODE_RF_16Jan2011/umc130nm/rf/Designkits/Cadence/Models/Spectre/Monte_Carlo/L130E_HS12_V241_MC_CORNER.lib.scs section "mc"
  • Doing DRC/LVS/PEX with cadence virtuoso
    • Use DRC Rule file from /srv/holl/pratap/cadence/foundry_data/calibre_ruledecs/Latest(Dec-2010)/DRC/130nm_merged_mixedmode_1P8M2T-Dec_2010.cal
    • Click on 'Load' once you have browsed to select the DRC rules file.
    • Also create a new directory for the "drc run directory". Else it will clutter the working directiry you are using.
    • Minimum ME1 spacing should be 0.16
    • For PEX, the rule file is /data/raiddisk/pratap/cadence/foundry_data/calibre_ruledecs/Latest(Dec-2010)/LPE/G-DF-MIXED_MODE_RFCMOS13-1P8M-MMC-FSG-L130E-CALIBRE-LVS-2.3-P6.txt
    • But for LVS, the rulefile is /srv/holl/pratap/cadence/foundry_data/calibre_ruledecs/Latest\(Dec-2010\)/LVS/G-DF-MIXED_MODE_RFCMOS13-1P8M-MMC-FSG-L130E-CALIBRE-LVS-2.3-P6.txt/
    • While doing PEX select format as SPECTRE (in output tab) -- this generates 3 .pex files
    • To speed up the run in the 'Run Control' tab select the 'Multi-threaded' option