E3 239 Jan 2015

From Microwiki
Jump to: navigation, search

Please fill in your name and email using this link below: Registration Form

References:

R1: Low Power Methodology Manual for System-On-Chip Design, Michael Keating, David Flynn, Robert Aitken, Alan Gibbons, Kaijian Shi, Springer 2007 (pdf IISc intranet only)

Midterm 1
Final Project
Final Question Paper
Answer to Q2 : Pg 1; Pg 2 (Courtesy Jeyaraj Desai)
Answer to Q5 (Courtesy Kavya Sharat)
Answer to Q12


1: Power, Heat, Energy in computing slides / video

Read: Aaron Carroll et. al., "An Analysis of Power Consumption in a Smart Phone", Proceedings of 2010 Usenix.

2: Standard Power Reduction techniques. slides / video

Read: R1 Chapter 1 & 2

3: Multi Voltage Design. slides / video

Read: R1 Chapter 3
Read: S. Lutkemeier et. al., "A Subthreshold to Above-Threshold level shifter comprising a Wilson Current Mirror", pdf
Read: Wooters S. N. et. al., "An energy-efficient sub-threshold level converter", pdf
Read: Zhou et. al., An Ultra-Low Voltage Level Shifter ..., IEEE TCAS-I, Early Access pdf

4: Dynamic Voltage Scaling slides/video
Read: R1 Chapter 9 & 10

5: Adaptive Voltage Scaling, video
Read: Nakai, et. al., Dynamic Voltage and Frequency Management...., IEEE JSSC, Jan 2005.
Read: Ikenaga et. al., A 27% Active-Power-Reduced..., IEEE JSSC April 2012.

6: In-Situ Critical Path Monioring, video
Read: Das et. al., A self-tuning DVS Processor ..., IEEE JSSC April 2006

7: Fundamental Limits to voltage scaling, video
Read: Alioto, M., “Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial,” in print on IEEE Trans. on Circuits and Systems – part I, vol. 59, no. 1, 2012.
Read: David Bol, Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS, Journal of Low Power Electronics and Applications, 1(1), 2011.

8: Practical Limits to Voltage Scaling, video
Read: Jain, S. et. al., A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS, ISSCC 2012.

9: Circuit Techniques for Ultra Low voltage, video

10: Ultra Low Voltage SRAM Cell, video
Read:, Takeda, et. al., A read Static Noise Margin Free SRAM cell for low-VDD and high speed applications, IEEE JSSC, vol 41, no.1, Jan 2006
Read:, Calhoun, B. et. al., A 256-Kb 65-nm sub-threshold SRAM design for ultra low voltage operation, IEEE JSSC, vol. 42, no. 3, March 2007

11: Low Voltage SRAM Write, video
Read:, Qazi, et. al., Challenges and Directions for Low Voltage SRAM, IEEE Design & Test of Computers, Jan/Feb 2011

12: On-chip power measurement: video
Read: Jotwani et. al., An x86-64 core in 32nm SOI CMOS, IEEE JSSC Jan 2011
Read: McGowen et. al., Power and Temperature control in a 90nm Itanium Processor, IEEE JSSC Jan 2006

13: On-chip power measurement - 2: video
Read: Mehta et. al., Dynamic Supply and Treshold Scaling with in-situ power monitor, IEEE TVLSI, May 2012
Read: Ramdass, Y., et. al., Minimum Energy Tracking Loop ...., IEEE JSSC, Vol. 43, No. 1, Jan 2008.
Read: Sagar, G.V., et. al., All Digital Energy Sensing for Minimum Energy Tracking, IEEE Transactions on VLSI, 2014


14: Power Gating
Read: R1 Chapters 4,5,6,7

15: Case Studies
Read: 1. Myers, et. al., An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM Cortex-M0+ Subsystem in 65nm CMOS for WSN Applications, ISSCC Feb 2015.
Read: 2. W. Lim et. al., Batteryless Sub-nW Cortex-M0+ Processor with Dynamic Leakage-Suppression Logic, ISSCC Feb 2015
Read: 3. V.K.Singhal et. al., A 10.5μA/MHz at 16MHz Single-Cycle Non-Volatile Memory-Access Microcontroller with Full State Retention at 108nA in a 90nm Process, ISSCC Feb 2015