E3 239 Jan 2014 Advanced VLSI Circuits

From Microwiki
Jump to: navigation, search

Timings: Tue-Thur-Fri 8-9am, ECE 1.08
First lecture: Jan 8 2014, ECE 1.08, 2pm

Topics: Embedded memories, High Speed Interfaces

Instructors: Bharadwaj Amrutur, Raviprasad Kuloor (IBM), Giri Rangan (IBM), Rahul Rao (IBM) and Janakiraman V (IBM)
TA: K R Viveka

Important Updates

  • 24th Jan (Fri) -- Assignment 1 Submission date
  • 18th Feb (Tue) -- Assignment 2 Submission date
  • Rescheduled: 28th Feb (Fri) 2:00 PM to 4:00 PM -- Test 1 on eDRAM, SRAM and Introduction to Probability and Random Variables -- Open Book Test
    Solutions to Test 1
  • There will be no Class on 13 Mar 2014 (Thur)
  • Lab demo on 18th March (Mon) 12:30PM to 1:30PM
  • 18 Mar 2014 (Tue) Class in EC 1.07 -- due to renovation work in EC 1.08
  • 21 Mar 2014 (Fri) Project Review meeting 11AM -- 1PM
  • 18th Mar (Tue) -- Assignment 3 Submission date
  • 25th Mar (Tue) -- Assignment 4 submission date
  • 4th April 2014 (Fri) 2PM - 4PM -- Test on High Speed Serial links in EC 1.08
  • 12th April 2014 (Sat) 11AM - 1PM -- 2nd Project Review Meeting
    Expected Results: Brief Overview, Initial performance numbers (speed, power, leakage-power, retention time), Issues, Modelling plan (critical-path), Future Plans
  • 28th April 2014 (Mon) 2PM-5PM -- Final Project Demo and Submission
  • The Lab has been setup in "Wi Com Net lab", located on the 1st floor of ECE Main Building (opposite the ECE Library), to enable students to work on course projects.
    The machines have Cadence Virtuso (IC616) and Spectre simulator (MMSIM121) installed on them with UMC 65nm libraries setup.
    Please contact Dr. Pratap for any further information regarding labs.
    Access to the lab may be obtained by contacting Gopalaiah Sir
    A rough tutorial on using IC616 is available here. This should help you get started


Summary of Lectures

Lecture 1: 8th Jan: Prof. Bharadwaj Amrutur
Introduction to course
Related presentation

Lecture 2: 9th Jan: Raviprasad Kuloor (IBM)
Memory hierarchy, Scaling -- SRAM, eDRAM, DRAM -circuit and layout structure, Write Operation
Lecture slides

Lecture 3: 10th Jan: Raviprasad Kuloor (IBM)
Read Operation, Cell transfer ratio, Sense-amplifier operation, Segmentation (WL and BL), Sense-amplifier -- direct sensing -- differential sensing, Micro sense amplifiers, Noise coupling mechanisms
Papers: Barth JSSC Jan 2011, Barth JSSC Jan 2008

Lecture 4: 16th Jan: Raviprasad Kuloor (IBM)
Micro Sense Amplifier Evolution, Micro Sense Amplifier Architecture, Data Sense Amplifiers, Redundancy (brief introduction), Noise -- Coupling from neighboring BLs -- Twisting in layout to ensure equal coupling on differential BLs
Papers: Barth JSSC Jan 2011, Barth JSSC Jan 2008

Lecture 5: 17th Jan: Raviprasad Kuloor (IBM)
Wordline drivers and level translators, Challenges in eDRAM design -- Retention time -- Floating gate effects, eDRAM vs SRAM, Timing diagrams

Lecture 6: 21st Jan: Giri Rangan (IBM)
Introduction to High Speed serial links -- Design trends and Challenges
Related presentation
Longer version of presentation -- 182 slides

Lecture 7: 23rd Jan: Giri Rangan (IBM)
Continued introduction to basics -- Signaling trends, Driver options, PLL clock transport issues, Receiver amplifier equalization
Related presentation
Book Chapter explaining presentation material

Lecture 8: 24th Jan: Giri Rangan (IBM)
Transmitter Channel Impairments, Impulse response, Eye-diagram, DFE and FFE -- brief introduction and FFE impact.
Related presentation -- Slides 16-20
Meghelli ISSCC 2006 -- paper referenced in slides

Lecture 9: 28th Jan: Giri Rangan (IBM)
Receiver Architecture, VGA, T-coil compensation network, Phase rotator requirements, DFE
Related presentation -- Slides 21-22

Lecture 10: 30th Jan: Rahul Rao (IBM)
SRAM cell types, System floorplan driven constraints, 6T cell - Read, Write and Hold, Sense-amplifier, Hierarchical Bitlines, Interleaved-layout -- Half select issues
Reference paper for SRAM section
Lecture Slides

Lecture 11: 31st Jan: Rahul Rao (IBM)
Review of bit-interleaving, SRAM-cell modifications for better noise performance -- Sizing, Multi-Vth options, Asymmetric design (Halo implants), Adding transistors
Lecture Slides
Referenced Papers: L. Chang VLSI Symp. 2005, K Takeda ISSCC 2005, Seok VLSI Symp. 2008

Lecture 12: 4th Feb: Rahul Rao (IBM)
SRAM cell Noise Margins (NM), Characterization of NM, Variation effects on NM, Dynamic circuit techniques -- WL boost, BL negative drive, Cell voltage (Vcs) modulation
Lecture Slides

Lecture 13: 6th Feb: Rahul Rao (IBM)
BTI and impact on SRAMs, Pop Quiz on SRAMs
Lecture Slides

Lecture 14: 7th Feb: Project Discussion
BTI effects on Read performance, Power estimation overview, eDRAM Projects, HSS Projects
HSS Project options, Memory Project options

Lecture 15: 11th Feb: Janakiraman V (IBM)
Memory testing -- Fault Model and Testing patterns, Redundancy and BIST
Memory fault models and coverage patterns, Redundancy and BIST

Lecture 16: 13th Feb: Janakiraman V (IBM)
Basics of Probability
Statistical-Modeling poster

Lecture 17: 14th Feb: Janakiraman V (IBM)
Basics of Probability continued
Assignment sheet

Lecture 18: 18th Feb: Janakiraman V (IBM)
Basics of Probability continued -- Central Limit theorem

Lecture 19: 20th Feb: Janakiraman V (IBM)
Importance sampling
Referenced Paper

Lecture 20: 21st Feb: Janakiraman V (IBM)
Basics of Random process -- required for HSS lectures
Reference: Chapter 8 (in 2001 Edition) -- An Introduction to Analog and Digital Communications by Simon Haykins.

Lecture 21: 25th Feb:
Project discussion and Finalizing Test dates

No class on 27th Feb (IISc Holiday)

Test 1 on 28th Feb

Lecture 22: 4th Mar: Arun Umamaheswaran (IBM)
Data Recovery in Serial Communication -- Introduction, Jitter sources and classification, CDR - Introduction

Lecture 23: 6th Mar: Arun Umamaheswaran (IBM)
Simple CDR Implementation, Phase Detector architectures
Presentation Slides

Lecture 24: 7th Mar: Arun Umamaheswaran (IBM)
CDR in High Speed Serial Links

Lecture 25: 11th Mar: Arun Umamaheswaran (IBM)
CDR System -- PLL (with I and Q o/p at C2), Phase rotators (2 of them), Data and Edge sampling FF, Deserializer (o/p at C16), Alexander phase-detector, CDR control logic to control the phase rotators

Lecture 26: 14th Mar: Venkatasreekanth Prudvi (IBM) -- 11AM to 1PM
High Speed Serial Links
Presentation Slides

Lecture 27: 18th Mar: Giri Rangan (IBM)
CML equalizer implementation, Receiver Architectures overview

Lecture 28: 20th Mar: Giri Rangan (IBM)
Receiver Analog circuits

Lecture 29: 21st Mar: Rajesh Cheeranthodi (IBM)
Phase Interpolator
Hand-Written Notes

Lecture 30: 25th Mar: Giri Rangan (IBM)
Receiver architecture

Lecture 31: 27th Mar: Giri Rangan (IBM)
Receiver clocking scheme

Lecture 32: 28th Mar: Rajesh Cheeranthodi (IBM)
FFE, DFE, VGA, Continuous time linear equalizer (CTLE) -- Low-pass based, high-pass based, RC-Shunt peaking amplifier, DAC for gain, peaking, and offset programmability

Lecture 33: 1st Apr: Giri Rangan (IBM)
Transmitter SST driver -- impedance matching and caliberator (R-CAL)

Lecture 34: 3rd Apr: Giri Rangan (IBM)
System description and Testing


Assignments and Project

  • Assignment 1 -- Due on 24th Jan (Fri)
    Referenced Paper
  • Tutorial/Assignment 2 on Basics of Probability theory -- Due on 18th Feb (Tue)
  • Assignment 3 -- Due on 18 Mar 2014 -- 1-page report on Jitter tolerance in CDR and it's characteristics (include only 1 figure)
    1-page report on Bath-tub curve (relevant paper will be uploaded shortly)
  • Assignment 4 -- Due on 25 March 2014 (Tue)-- SST vs CML comparison (Spec. 15 Gbps, vdd=1.2 V with 5% tolerance, 3-tap equalization) -- Please mail the assignment to Viveka

Project

Options: HSS Project options, Memory Project options

Tools:
Spice models for 16nm process from ASU (model name has been changed)
Please refer to DVLSI course webpage E0 284 Aug 2013 for further information regarding tools.


Interesting articles