E0 284 Jan 2013

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CMOS VLSI Design, 4th Edition, West and Harris


Digital Integrated Circuits, Rabaey, Nikolic, Chandrakasan


Electric Editor (Download Java binary version)

Java run time environment (JRE) from Oracle

LTSpice from Linear Technologies (this is a windows executable)

Spice models for 16nm process from ASU (model name has been changed)

Wine to run windows program on a unix platform

Example wrapper file for including stimulus etc commands lab1.cir

Jelib file to be used for the labs E0284.jelib

Electric/LTSpice handout

Tutorial for Electric Editor


1. Overview

2. Transistor Basics

3. Transistor Advanced
Optional: MOS Technology Evolution for Circuit Designers by Dr. Alvin Loke (AMD) Video,Slides.

4. Delay Basics

5. Logical Effort

6. Minimizing Delay

Lab1: Find the FO4 Delay for VDD=0.9V, 0.6V, 0.35V for T=25C and 125C in the 16nm process using the PTM spice models. Turn in a single sheet of paper with the table for the above values. Write you name/SRNO/email address. Due date, Monday Jan 27 2013 in class.

Lab 2

7. Minimizing Delay (contd.)

8. Combinational Gate Design

9. Domino circuits

10. Circuit Concepts

12. Clocking

13. Clock Timing constraints

14. Latch based design

15. Pulsed Clocking

16. Asynchronous Techniques

Quiz 2

Final Project

17. Wires

18. Wires (contd.)

19. Basics of Memories

19. SRAMs

19. DRAMs and CAMs