E0-286: Test and Verification of SOC Designs

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Schedule: Tuesday 11:10AM - 1:10PM
Venue: Room no. 1.08, ECE Dept.

Quiz 1: Open book test 11:15AM - 12:15PM, 13th September 2012 in ECE 1.08
Syllabus covered till and including 4th September 2012.

Mid-sem Exam: 9th October 2012.

Main references:

  1. M.Abramovici, M.A.Breuer and A.D.Friedman, Digital Systems Testing and Testable Design, IEEE Press. (Indian edition available).
  2. M.L.Bushnell and V.D.Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Kluwer Academic Publishers.
  3. D.Gizopoulos, (Editor), Advances in Electronic Testing: Challenges and Methodologies, Springer, 2005.

Other references: Media:refs.pdf

Course outline: Media:outline.pdf

Lecture Slides

  • Lecture 1: 9th August 2012: Introduction to the course Media:08-09.pdf
    • Design and test complexity, SOC design flow, Architecture specification, RTL design and verification, Synthesis, Static Timing Analysis (STA), Physical design
    • Verification v/s Test, Testing IPs, Digital Logic, Memories, Analog IPs, SoCs
    • Test effectiveness metrics and economics
  • Lecture 2, 3: 14th, 21st August 2012: Background material Media:0814.pdf
    • Cost of test, Failure Models, Terminology: Yield, Coverage, DPPM, FIT rate, Reliability, Defect, Fault, Error, Outlier
    • Test cost tradeoffs and reducton, Diverse markets & Apportioned Quality Cost, DPPM Calculations
    • SOC Test scheduling options, Volume of test data and Scatter plots, Cost v/s coverage, Test power concerns, Four quadrant analysis
  • Lecture 3, 4, 5: 21st, 28th August 2012, 4th September: Media:0904.pdf
    • Examples of DFT, Defects, Faults and Errors, Fault models and sizes, Fault list pruning
    • Additional faults in memory, Stuck-at fault model, Complexity of Test generation, ATPG & Bounds on number of input test patterns
    • Scan implementation & Compression, Launch and Capture at-speed, IDDq Current test (Not covered), Two pattern tests: Launch after initialization
    • Assignments (Foil #33) not for grading.
  • Lecture 6: 6th September: Media:E0-286.06Sep.vrd.pdf
    • Scan design: Introduction, Requirements, Types of scan, Optimizations
    • Managing scan for IPs and SOCs.
    • Assignmnets (Foil #25) not for grading.
  • Lecture 7: 11th September: Media:E0-286.11Sep.vrd.pdf
    • Delay Test: Launch Off Capture, Launch Off Shift, Path Delay, Small Delay Defects
    • Delay test with multiple clock domains
    • Scan architectures for coverage enhancement
    • Testing memory interface logic
    • Assignments (Foil #27) not for grading.
  • Lecture 8: 18th September: Media:E0-286.18Sep.vrd.pdf
    • Memory test: Functional fault models
    • Test algorithms
    • BIST architecture
    • Memory repair
  • Lecture 9: 25th September
    • Discussion of Quiz-1 solutions
  • Lecture 10: 4th October
    • Q&A, Discussion of Assignments
  • Lecture 11: 16th October
    • Discussion of Medsem exam solutions
  • Lecture 14, 15: 25th, 30th October: Media:TestPower_Oct25.pdf
    • CMOS Power Consumption basics
    • Test Power Problem
    • Power Estimation and Models
    • Power Analysis Flows
    • Power optimizations for DFT, Gating for combo cloud, Scan segmentation.
    • References Last three foils
    • Assignment 1: Due 6 November 2012 Media:Assignment_1.pdf
  • Lecture 12, 13, 16: 18th, 23rd October, 6th November Media:1106.pdf
    • Scan compression and BIST
    • Assignment 2: Due 24 November 2012. Refer last foil for assignments.
  • Lecture 19: 27th November
    • Analog DFT methods
    • Verification